Charge trapping non-volatile memory devices (NVM devices) such as SONOS (silicon dioxide—silicon nitride—silicon dioxide—silicon) and SHINOS (silicon—high K—silicon nitride—silicon dioxide—silicon) memory devices are considered suitable candidates to enable flash memory devices in CMOS generation devices of the 45 nm node and smaller. SONOS and SHINOS memory devices exhibit relatively reduced program and erase voltages. Moreover, these devices are relatively easy to integrate with CMOS logic in case of embedded NVM devices.
Planar NVM devices, typically based on MOSFET devices, are hardly scaleable beyond the 45 nm node due to short channel effects. As known in the art, an improvement of device characteristics can be obtained by application of a finFET structure.
In a finFET, on top of an insulating layer a (relatively narrow) silicon line (a fin) is created between a source region and a drain region to serve as a channel. Next a line-shaped control gate is created which crosses the fin. Separated by a thin gate oxide film from the fin, the control gate surrounds (in cross-section) both the sidewalls and the top of the fin, which allows a relatively large field effect by the gate on the fin channel.
A finFET-based NVM device could comprise either a charge trapping stack such as for example either an ONO layer stack (silicon oxide—silicon nitride—silicon oxide) or a charge trapping layer stack of a high K material, a layer of silicon nitride and a layer of silicon dioxide. In such a charge trapping stack the silicon nitride layer is arranged for controllably holding electric charge.
Typically, the charge trapping stack could cover both the side walls and the top of the silicon fin.
The quality of SONOS non-volatile memory and generally, non-volatile memory based on charge trapping stacks is sensitive to the thickness of the bottom oxide layer adjacent to the channel region. The bottom oxide is usually a grown oxide which may have a superior quality over oxide layers that are formed by deposition. Typically, grown oxide has a lower density of defects, for example, pin holes.
Nevertheless, a small variation of the oxide thickness affects the tunneling of electrons through the bottom oxide significantly. The tunneling current of various tunneling mechanisms (e.g. direct tunneling, Fowler-Nordheim, modified Fowler-Nordheim) is known to exhibit an exponential dependency on the thickness of the bottom oxide. A small variation in the bottom oxide results in a significant variation of the charge injected into the nitride layer and hence in a variation of the threshold voltage (for programming or erasing).
Since charge can be localized in a nitride layer, a variation of bottom oxide thickness within a non-volatile memory cell can lead to local variations of trapped charge and to local variations of threshold voltage. When the bottom oxide thickness is not uniform over the channel region, this may result in a partly programmed cell area with a higher threshold voltage and a remaining (not programmed) cell area with a lower threshold voltage.
Clearly, this has undesirable effects on the characteristics of a finFET SONOS memory device, where the bottom oxide is grown after the formation of the fin and the fin has a number of crystal faces with edges (transition zones) that have different crystallographic orientations. This results in a programmed channel region with locally different threshold voltages; it may degrade the sub-threshold characteristics of a programmed non-volatile memory device, and makes the (electronic) programming window subject to significant variations.